1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a method for fabricating a semiconductor device.
2. Discussion of the Related Art
In order to increase an operation frequency of a device, it is in general required to shorten a length of a gate in a semiconductor device. However, further shortening of the gate length which is about 1 .mu.m causes a gate resistance to increase due to a smaller aspect ratio. Therefore, in order to prevent increase of the gate resistance while shortening the gate length further, a method in which a section of the gate is formed to have a T form is mostly used.
A conventional method for fabricating a semiconductor device will be explained with reference to the attached drawings. FIGS. 1a and 1b illustrate sections showing one example of the steps of the conventional method for fabricating the T form gate.
Referring to FIG. 1a, first, second and third resists 2, 3 and 4 are formed in succession on a substrate 1, and predetermined regions of which are selectively exposed. The first and third resists are formed of materials of which expose sensitivities are the same, and the second resist is formed of a material of which expose sensitivity is higher than the expose sensitivities of the first and third resists 2 and 4. That is, the second resist 3 is formed of a resist which can cause an exposure with a little dose.
Referring to FIG. 1b, the first, second and third resists are selectively developed to form resist patterns. In this time, the second resist 3, of which expose sensitivity is higher than the expose sensitivities of the first and third resists 2 and 4, is developed more in terms of region. On an entire resultant surface having the resist patterns formed thus, a metal is deposited and subjected to a lift off process to form the T form gate electrode.
FIGS. 2a-2c illustrate sections showing another example of the steps of the conventional method for fabricating the T form gate.
Referring to FIG. 2a, first and second resists 11 and 12 are formed on a substrate 10 in succession, and predetermined regions of which are exposed for the first time to a width of about 0.1. .mu.m each. The first resist 11 has an expose sensitivity that is higher than the expose sensitivity of the second resist 12.
Referring to FIG. 2b, the first and second resists 11 and 12 are exposed for the second time to a width of about 1 .mu.m each including the regions which were exposed for the first time. As shown in FIG. 2c, the exposed first and second resists 11 and 12 are developed to form resist patterns. On an entire resultant surface of the substrate having the resist patterns formed thereon, a metal is deposited and subjected to a lift off process to form the T form gate electrode.
However, the aforementioned conventional method for fabricating a semiconductor device has the following problems.
The obtaining of a gate length of 0.1 .mu.m from two or three layered resists having a total thickness of about 6000.ANG..about.7000 .ANG. makes the fabrication process and its reproducibility difficult.